Via Stub Effect

Differential Pair Routing | PCB Design Guidelines

How BGA Breakout Regions Compromise Differential Pair Impedance and How to Fix

In high-speed PCB design, BGA breakout regions often compromise differential pair impedance, causing signal reflection and jitter. This page explains why these impedance discontinuities occur and provides proven fixes—including anti-pad optimization, via backdrilling, and trace geometry tuning—to maintain 100Ω or 90Ω control for reliable high-speed performance. Why BGA Breakout Regions Compromise Differential Pair Impedance 1.1…

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Power Integrity | Signal Integrity

Via Inductance Optimization for Better Power Integrity PCB Performance

Optimizing via inductance is critical for achieving better power integrity PCB performance in high-speed designs. This pillar page covers the essential strategies, from geometry tuning to advanced simulation, to help you reduce PDN impedance and improve system reliability. Understanding Via Inductance and Its Impact on PDN What is Via Inductance? Vias are not ideal conductors;…

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Return Path | Signal Integrity

How Vias Create a Gap in Return Path PCB Design and What to Do

In high-speed PCB design, vias create a gap in return path continuity, degrading signal integrity. This article explains how vias disrupt the return path and provides expert solutions for reliable B2B PCB manufacturing. How Vias Create a Gap in the Return Path PCB Design The Physics of Return Path Discontinuity When a high-speed signal transitions…

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Return Path | Signal Integrity

Return Path PCB Design for DDR5 Data Strobe Reference Plane Requirements

Master DDR5 PCB design with a deep dive into the Return Path PCB Design for DDR5: Data Strobe Reference Plane Requirements. Learn about return path discontinuity, via optimization, and stack-up strategies for reliable high-speed signal integrity in your next PCB project. The Criticality of the Return Path in DDR5 The transition from DDR4 to DDR5…

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Reflection and Termination | Signal Integrity

Reflection in Transmission Line Analysis in Cadence Sigrity A Practical Guide

Master Reflection in Transmission Line Analysis for high-speed PCB designs using Cadence Sigrity. This practical guide covers TDR simulation, impedance discontinuities, termination strategies, and step-by-step workflows to ensure signal integrity for your advanced PCB projects. Understanding the Physics of Reflection in High-Speed PCB Before diving into software, you must grasp the fundamental principles. Reflection is governed by…

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Impedance Control | Signal Integrity

How Via Transitions Ruin Impedance Control PCB and How to Fix Them

In high-speed PCB design, via transitions ruin impedance control by introducing capacitance and inductance that create signal reflections. This pillar page explains the physics, real-world impacts, and proven fixes for maintaining consistent 50Ω impedance through via structures. The Physics of How Via Transitions Ruin Impedance Control PCB Capacitive and Inductive Nature of Vias A via…

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